1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device that uses memory cells having electric charge accumulation layers made of insulating films.
2. Description of the Related Art
In a NAND flash memory having floating gates, as the miniaturization is being advanced, there arise problems of interference among neighboring cells and difficulty in burying insulating films between cells. Accordingly, it becomes necessary for this type of flash memory to change the structure of memory cells (cell transistors).
Memory cells considered to be most promising for a gate length around 20 nm are those having electric charge accumulation layers made of insulating films. These memory cells are called MONOS (metal/oxide-film/nitride-film/oxide-film/semiconductor), which are realized by forming gate stack structures on the channels between source/drain diffusion layers on a Si substrate. The gate stack structure are composed of a tunnel insulating film to pass through electric charges for writing or erasing data, a silicon nitride film that functions as an electric charge accumulation layer, a silicon oxide film that functions as an insulating film for preventing currents from flowing, and a gate electrode formed thereon, etc. Since this MONOS memory cell is configured in the form of a flat cell, above-described problems raised in the conventional floating gate type NAND flash memory can be solved.
However, the MONOS memory cell has some performance problems to be solved, such as the magnitude of the variation of the threshold voltage (abbreviated as Vth, hereinafter), endurance characteristics, data retention characteristics, etc. In addition, there is a problem that the threshold voltage of the MONOS memory cell is not compatible with the threshold voltage which is necessary for a NAND-type flash memory cell used for mass storage.
That is, the threshold voltage of the MONOS memory cell is often in the range of Vth>0 both after writing and after erasing data. This fits into the range of threshold voltage required in a NOR flash memory, but is different from that of a NAND flash memory which should fulfill Vth>0 after writing data and Vth<0 after erasing data. Actually, even in a MONOS memory cell whose performance is considered to be the highest, although Vth after writing data can be made sufficiently large, Vth of sufficiently large negative value cannot be obtained as the threshold voltage after erase operation (for example, a document 1 (A. Chin, C. C. Laio, C. Chen, K. C. Chiang, D. S. Yu, W. J. Yoo, G. S. Samudra, T. Wang, I. J. Hsieh, S. P. McAlister, and C. C. Chi, “low voltage High Speed SiO2/AlGaN/AlLaO3/TaN Memory with Good Retention”, IEDM Tech. Dig. pp. 165-168 (2005))). Accordingly, it is difficult to employ the MONOS memory cell for a NAND flash memory, although the MONOS is suited for a NOR flash memory.
In employing the MONOS memory cell for a NAND flash memory, there is a problem that the threshold voltage has to be adjusted. So as to adjust the threshold voltage, there may be a method of adjusting the dopant impurity concentration in the channel regions of a Si substrate. As the miniaturization of memory cell is being advanced, the short channel effect becomes noticeable, and it is necessary to increase the neutral threshold voltage (initial threshold voltage under which data is not written or erased) so as to suppress the short channel effect. On the other hand, as described above, since the neutral threshold voltage is decreased in the operation of a NAND flash memory, discrepancy between the demands for the neutral threshold voltage becomes severe as the miniaturization is being advanced. That is, the above-described problem cannot be solved by adjusting the dopant impurity concentration of the channel regions.
In this way, there is the problem that the threshold voltage of the conventional MONOS memory cell does not fit into the threshold voltage required in the operation of a NAND flash memory. Even though an attempt is made to solve the problem by adjusting the substrate dopant impurity concentration, it is extremely difficult to employ the method for the miniaturized NAND flash memory.